IC_RESTART_EN=DISABLED, TX_EMPTY_CTRL=DISABLED, IC_10BITADDR_MASTER=ADDR_7BITS, STOP_DET_IFADDRESSED=DISABLED, MASTER_MODE=DISABLED, IC_SLAVE_DISABLE=SLAVE_ENABLED, IC_10BITADDR_SLAVE=ADDR_7BITS, RX_FIFO_FULL_HLD_CTRL=DISABLED
I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.
| MASTER_MODE | This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with ‘1’ then bit 6 should also be written with a ‘1’. 0 (DISABLED): Master mode is disabled 1 (ENABLED): Master mode is enabled |
| SPEED | These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 1 (STANDARD): Standard Speed mode of operation 2 (FAST): Fast or Fast Plus mode of operation 3 (HIGH): High Speed mode of operation |
| IC_10BITADDR_SLAVE | When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. 0 (ADDR_7BITS): Slave 7Bit addressing 1 (ADDR_10BITS): Slave 10Bit addressing |
| IC_10BITADDR_MASTER | Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing 0 (ADDR_7BITS): Master 7Bit addressing mode 1 (ADDR_10BITS): Master 10Bit addressing mode |
| IC_RESTART_EN | Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED 0 (DISABLED): Master restart disabled 1 (ENABLED): Master restart enabled |
| IC_SLAVE_DISABLE | This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. 0 (SLAVE_ENABLED): Slave mode is enabled 1 (SLAVE_DISABLED): Slave mode is disabled |
| STOP_DET_IFADDRESSED | In slave mode: - 1’b1: issues the STOP_DET interrupt only when it is addressed. - 1’b0: issues the STOP_DET irrespective of whether it’s addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1’b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). 0 (DISABLED): slave issues STOP_DET intr always 1 (ENABLED): slave issues STOP_DET intr only if addressed |
| TX_EMPTY_CTRL | This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. 0 (DISABLED): Default behaviour of TX_EMPTY interrupt 1 (ENABLED): Controlled generation of TX_EMPTY interrupt |
| RX_FIFO_FULL_HLD_CTRL | This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. 0 (DISABLED): Overflow when RX_FIFO is full 1 (ENABLED): Hold bus when RX_FIFO is full |
| STOP_DET_IF_MASTER_ACTIVE | Master issues the STOP_DET interrupt irrespective of whether master is active or not |